This invention relates to Complementary Metal Oxide Silicon (CMOS) Electrically Programmable Read Only Memory (EPROM) and CMOS EEPROM (Electrically Erasable and Programmable Read Only Memory) devices, which are especially suitable for embedded applications.
In many applications, particularly in System-on-Chip (SoC) applications, designers want to have a certain number of embedded non-volatile memory devices on the microprocessor or Application-Specific Integrated Circuit (ASIC) chips. The preferred approach for meeting this need is to provide embedded non-volatile memories that require little or no additional process cost to the base logic technology. Often, the additional requirements for such embedded non-volatile memories are high density, i.e. small cell size, low power, and high speed.
In a regular CMOS logic process, non-volatile memory devices are typically made using charge storage in a floating gate electrode. In general, it takes a lower voltage to inject hot electrons from silicon into a floating gate electrode than to inject electrons from silicon into a floating gate electrode by Fowler-Nordheim tunneling. As a result, for high-speed and low-voltage operation, hot electron injection is typically used.
Floating gate Field Effect Transistors (FETs) including a control gate are well known. A floating gate electrode differs from a control gate electrode in that it has no direct electrical connection to any external component and is surrounded by isolation on all sides. In a typical floating gate FET including a control gate, the control gate is positioned on top of the floating gate. The presence of a control gate electrode enables an FET device to function as a regular FET, while a floating gate electrode collects and stores injected electrons or holes. The floating gate electrode provides a method for changing the threshold voltage needed to pass a charge from the source region of the FET to the drain region thereof. The presence of the control gate electrode adds control to the injection of charges into and out of the floating gate region of the FET, thus enabling the FET device to function as an electrically programmable or reprogrammable memory device depending upon other factors as explained below.
Source-side injection flash cells or split gate flash cells are commonly used as embedded flash memories. In a split gate cell, the floating gate overlies only a portion of the channel and the control gate electrode overlies both the floating gate electrode and the remainder of the channel. In other words, there are two transistors in series between a source and a drain. One relatively popular flash cell employs oxidized polysilicon to create sharp points in the polysilicon in order to enhance the electric field. This in turn allows erasure at lower voltages and provides for thicker dielectric layers between the floating gate electrode and the control gate electrode. The LOCalized Oxidation of Silicon (LOCOS) process is commonly used for fabricating such cells to form an insulator cap over the polysilicon of the floating gate electrode. The LOCOS process creates sharp points on the floating gate electrode, resulting in a bird's beak structure.
Nevertheless, the existing flash memory cells exhibit two major shortcomings which are high programming voltage required and non-planar cell topography due to the presence of the floating gate electrode.
In a floating gate device, electrons are injected into the floating gate electrode, either by hot electron injection or by electron tunneling (Fowler-Nordheim or F-N tunneling). In the case of hot electron injection, it is well-known that it is much more efficient to use avalanche hot electron injection using a p-channel FET device than to use channel hot electron injection using an n-channel FET device. A paper by Hsu et al. entitled “A High-Speed Low-Power P-Channel Flash EEPROM Using Silicon-Rich Oxide as Tunneling Dielectric,” 1992 Int. Conf. Solid-State Devices and Materials, Extended Abstract, pp. 140-142 (1992) includes experimental evidence that it is desirable to use both a p-channel floating-gate FET as the memory element and avalanche hot electron injection as the programming mechanism.
For embedded applications, it is desirable to use an access or select transistor connected in series with the memory element to form the non-volatile memory cell. While adding a select transistor adds area to the memory cell, the use of a select transistor avoids many issues of operation of a true single-device memory cell with no access transistor. For example, such an access transistor guarantees that there is no over-erase problem, and avoids disturbing the non-selected cells.
For the select transistor, it is desirable to use an n-channel FET, instead of a p-channel FET, because an n-channel FET typically has twice the performance as a p-channel FET due to higher electron mobility. In other words, it is desirable to have a CMOS non-volatile memory device where the n-channel FET is used as an access transistor and the floating-gate p-channel FET is used as the memory element.
U.S. Pat. No. 7,091,075 B2 of Chaudhry entitled “Fabrication of an EEPROM Device with SiGe Source/Drain Regions” shows a non-volatile memory device which employs an nFET and a pFET, but it is built using bulk CMOS devices, not SOI CMOS. The pFET is used as select device while the nFET gate electrode is floating and is used as memory device. The present invention teaches using a pFET, with its gate electrode floating, as the memory device, while the nFET is used as select device. A problem with such a device are first that a pFET select device has only about half the performance of a nFET select device and second that a floating-gate nFET used as memory device has much higher power dissipation compared with a floating-gate pFET employed as a memory device.
U.S. Pat. No. 6,841,447 of Logie entitled “EEPROM Device having an Isolation-Bounded Tunnel Capacitor and Fabrication Process” describes a memory element built using bulk CMOS devices, not an SOI CMOS consisting of both an nFET and a pFET, with the floating gate electrode of the pFET and the floating gate electrode of the nFET are connected together electrically. Also there is a control gate electrode “on top” of the connected floating gate electrode. A problem with such a device is that the resulting memory element, consisting of an nFET and a pFET, is significantly larger than the present invention where only the floating-gate pFET is used as memory element. In contrast to Logie, according to the present invention, only the pFET, with its gate electrode floating, is used as memory element.
U.S. Pat. No. 5,016,217 of Brahmbhatt entitled “Logic Cell Array Using CMOS EPROM Cells Having Reduced Chip Surface Area” describes an Electrically Programmable Read Only Memory (EPROM) memory cell including a serially connected Complementary Metal Oxide Silicon (CMOS) transistor pair with common floating gate electrodes and common control gate electrodes. A third n-type floating gate FET is used to program the memory cell. The floating and control gates of the third transistor are connected to the common floating and control gates, respectively, of the CMOS transistor pair. A tri-state memory cell can be provided by connecting the source of the p-channel transistor of the CMOS pair to the common control gates. An EPROM cell is described including the pFET and the nFETs in the cell all of which have a floating gate. Those floating gates are all electrically connected together. Each FET has a control gate above the floating gate. According to the present invention, the nFET does not have a floating gate, while the pFET has a floating gate but without a control gate. A problem with such a device is that a very large area is taken up by the floating-gate memory element which covers all three transistors. In addition, Brahmbhatt is built using bulk CMOS devices which have an additional problem that the pFET is built using an n-well and the nFETs are built using a p-well. Since the well regions are larger than the actual pFET and nFET devices themselves, the resulting area taken up to build the Brahmbhatt memory device is significantly larger than the area of a memory device built in accordance with the present invention.
U.S. Pat. No. 5,886,376 of Acovic et al entitled “EEPROM Having Coplanar On-Insulator FET and Control Gate” describes an electrically erasable programmable read-only memory (EEPROM) which includes an FET and a control gate spaced apart on a first insulating layer. A second insulating layer is formed over the FET and the control gate and a common floating gate on the second insulating layer over the channel of the FET and the control gate, the floating gate thus also forms the gate electrode of the FET. The EEPROM devices may be interconnected in a memory array and a plurality of memory arrays may be stacked on upon another. In contrast, the present invention overcomes the problem of using a non-standard Silicon-On-Insulator (SOI) CMOS process to make EEPROM arrays with high areal density.
U.S. Pat. No. 6,215,689 B1 of Chorr entitled “Architecture, Circuitry and Method for Configuring Volatile and/or Non-Volatile Memory for Programmable Logic Applications” describes a memory device, states as follows: “Architecture, circuitry, and methods are provided for operating a high speed, volatile programmable logic integrated circuit using back-up non-volatile memory cells configured on an integrated circuit separate from the programmable logic integrated circuit. The lower density non-volatile memory cells can be formed on an integrated circuit using fabrication steps similar to those used to form, e.g., EEPROM devices or, more specifically, flash EEPROM devices. The programmable logic integrated circuit includes high density, volatile memory cells integrated with high speed, low density configurable CMOS-based logic. By using two separate processing technologies on two separate and distinct monolithic substrates, and interconnecting the separate integrated circuits on a singular monolithic substrate, the advantages of non-volatility can be combined with a high speed programmable circuit. The pins extending from the programmable logic device can be mounted in various ways to corresponding receptors on a printed circuit board. The architecture, circuitry, and method thereby present a packaged device which inherently has the same characteristics as a single integrated circuit, yet is actually two integrated circuits having the benefits of non-volatility as well as the benefits of higher speed, higher density volatile logic blocks within a programmable logic device or complex programmable logic device.” In accordance with the present invention, the memory element is fully compatible with CMOS logic process, and both memory and logic elements are made on the same silicon chip. In Chorr memory elements and logic elements are made on different silicon chips by different process flows, with the problem that the device lacks the desirable attribute of integrating all the desired logic circuits and memory functions on a single chip.
U.S. Pat. No. 6,207,991 B1 of Rahim “Integrated Non-Volatile and CMOS Memories Having Substantially the Same Thickness Gates and Methods of Forming the Same” describes a method of forming non-volatile memory (e.g. an EEPROM device) and a bulk CMOS device (e.g. a RAM), not a SOI CMOS, on a single die or chip, and a structure formed by the method. In one embodiment, the control gate of the storage transistor as well as the isolation gate of the isolation transistor may be formed during the same manufacturing process step, and thus may be formed of the same gate polysilicon material and may have similar thickness. The memory device in the Rahim patent is an nFET device. A problem with such an nFET memory device is that it requires more power dissipation to program a floating-gate nFET than a floating-gate pFET. In the present invention, the memory device is a pFET device.
U.S. Pat. No. 6,498,371 of Krishnan et al. entitled “Body-Tied-To-Body SOI CMOS Inverter Circuit” describes an SOI CMOS inverter circuit in which the drain of each of an n-FET and a P-FET are electrically coupled to form an output of the inverter circuit by a silicide layer in combination with a body region formed in the SOI layer ties. At the same time, however, the body regions remain floating electrically so that the benefits of SOI are maintained.
To reduce cell area in bulk CMOS implementations, a p-FET is usually used for an access transistor instead of an n-FET. Such all p-FET bulk CMOS implementations are described in both U.S. Pat. No. 6,678,190 of Yang entitled “Single Poly Embedded EPROM” and U.S. Pat. No. 6,711,064 of Hsu entitled “Single-Poly EPROM”. U.S. Pat. No. 6,678,190 of Yang describes an erasable programmable read only memory comprising two serially connected P-type metal-oxide semiconductor (MOS) transistors wherein the control gate is omitted in the structure for layout as the bias is not necessary to apply to the floating gate during the programming mode. U.S. Pat. No. 6,711,064 of Hsu describes a single-poly EEPROM which includes a first PMOS transistor that is serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P-type substrate. The first PMOS transistor includes a floating gate, a first P+ doped drain region, and a first P+ doped source region. The second PMOS transistor includes a gate and second P+ doped source region. The first P+ doped source region of the first PMOS transistor serves as a drain of the second PMOS transistor. For erasing the single-poly EEPROM, an erase gate which extends to the floating gate is provided in the P-type substrate. A problem with such a device is that a pFET access transistor has only about half the performance of an nFET access transistor.
B Commonly assigned U.S. Pat. No. 7,244,976 of Cai et al. entitled “EEPROM Device with Substrate Hot-Electron Injector for Low-Power Programming” describes a low programming power, high speed EEPROM device adapted for large scale integration. The device comprises a body, a source, and a drain, plus it has means for injecting a programming current into the body. The hot carriers from the body enter the floating gate with much high efficiency. The drain current of the device, which is built on an insulator, with a bottom common plate, and a top side body, is controlled by the body bias. The device is adapted for SOI and thin film technologies.
FIG. 1A is a schematic diagram of a cross section of a prior art CMOS inverter 10 comprising an SOI nFET 11 and an SOI pFET 13. FIG. 1B is an electrical schematic diagram of the device of FIG. 1A. The inverter 10 is formed on a substrate 12 preferably composed of silicon, with a Buried Oxide (BOX) layer 14 formed on the top surface thereof. A left isolation oxide region 15L is formed over the BOX layer 14 on the left of the inverter 10; and a right isolation oxide region 15R is formed over the BOX layer 14 on the right of the inverter 10. An SOI layer composed of doped regions 16, 17, 18, 19, 20 and 21 is formed over the BOX layer 14 between left isolation oxide region 15L and the right isolation oxide region 15R. The nFET II is composed of an n+ doped source region 16, a p doped channel region 17 and an n+ drain region 18, which are formed on the top surface of the BOX layer 14 adjacent to the left isolation oxide region 15L. The pFET 13 is composed of p+ doped drain region 19, an n doped channel region 20 and a p+ source region 21 which are formed on the top surface of on the BOX layer 14 between the n+ drain region 18 and the right isolation oxide region 15R.
The nFET 11 includes a thin gate dielectric (silicon dioxide or other electrical insulating material) layer 23 formed over the p doped channel region 17 of the nFET 11 and a first gate electrode G1, which is electrically conductive, located above the thin gate dielectric layer 23.
The pFET 13 includes a second, thin gate dielectric (silicon dioxide or other electrical insulating material) layer 25, formed over the n doped channel region 20 of the pFET 13, and a second gate electrode G2, which is also electrically conductive, located above the second gate dielectric layer 25. The first and second gate dielectric layers 23 and 25 have thicknesses which are thin, as stated above, and are preferably substantially equal.
A first silicided contact 22 (S) is formed on the top surface of the source region 16 of the nFET 11. A second silicided contact 24, which is formed on the combined top surfaces of both the drain region 18 of the nFET 11 and the drain region 19 of the pFET short circuits the drains regions 18 and 19 together. A third silicided contact 26(S) is formed on the top surface of the source region 21 of the pFET 13. The first silicided contact region 22(S) and the second silicided contact region 24 are spaced away from the first gate electrode G1, and the second and third silicided contact regions 24 and 26(S) are spaced away from the second gate electrode G2.
Referring to both FIGS. 1A and 1B, the first silicided contact 22 connects reference potential Vss, i.e. ground voltage, which equals zero Volts, to the source region 16 of the nFET 11. The first gate electrode G1 is connected by line 28A to an input terminal VIN and to line 28B which connects to the second gate electrode G2, so that the first gate electrode G1 is electrically connected to the second gate electrode G2, with both of them being at the input potential VIN. The second silicided contact 24 is connected to an output terminal VOUT. The third silicided contact 26(S) is connected to a power supply terminal Vdd. Referring to FIG. 1C, the input and output voltages of the inverter 10 are related so that when VIN is in a logic state of “0” or has a value substantially equal to zero, VOUT is in a logic state of “1” or has a value substantially equal to Vdd, and when VIN is in a logic state of “1” or has a value substantially equal to Vdd, VOUT is in a logic state of “0” or has a value substantially equal to zero. These relationships are indicated in Table I below, as will be well understood by those skilled in the art.
TABLE IVINVOUT“0” or zero“1” or Vdd“1” or Vdd“0” or zero
FIG. 1D is a schematic diagram of a cross section of a prior art MOS FET EPROM device 30 comprising a bulk pFET 31 and another bulk pFET 33, without any n-FET devices, formed on an N-well 39. The N-well 39 is centered between the right edge of a left isolation oxide region 35L and the left edge of a right isolation oxide region 35R. The pFET 31, which is formed adjacent to the left isolation oxide region 35L, is composed of an p+ doped source region 32(S), an n doped channel region CH1 and the left half of a shared, p+ doped region 37. The pFET 33 is composed of the right hand half of the shared, p+ doped region 37, an n doped channel region CH2 and a p+ drain region 36 formed between the pFET 31 and the right isolation oxide region 35R. The shared, p+ region 37 is the source for the pFET device 33. For a pFET, the region with higher voltage is the source and the region with the lower voltage is the drain, visa versa for an nFET. For two pFETs in series, as in FIG. 1D, the highest voltage (Vdd) is applied to region 32(S), or the source of pFET 31, and the region 37 is the drain of pFET device 31 as well as the source of the pFET device 33. The p+ drain region 36 is the drain of pFET device 33.
As in FIG. 1A, the pFET 31 includes a thin gate dielectric (gate oxide) layer 23 formed over the first channel region CH1 of the pFET 31 and a third gate electrode G3, which is electrically conductive, located above the thin gate dielectric layer 23.
The pFET 33 includes a first thick gate dielectric (e.g. silicon oxide) layer 25F, formed over the n doped channel region CH2 of the pFET 33, and a first floating gate electrode FG1, which is also electrically conductive, located above the first thick gate dielectric layer 25F. The gate dielectric layer 23 and the first thick gate dielectric layer 25F have substantially different thicknesses with the first thick gate dielectric layer 25F being substantially thicker than gate dielectric layer 23, since the thick gate dielectric must be sufficiently thick to prevent leakage of charge stored on the floating gate FG1, as stated by the following references. U.S. Pat. No. 6,992,926 of Iwase et al. entitled “Driver Circuit for Semiconductor Storage Device and Portable Electronic Apparatus” states “For prevention of leakage of holding charges, the thickness of an insulating film isolating the floating gate from the channel region or the well region cannot be reduced to about 7 nm or less.” In addition, an article by Prinz et al entitled “Nonvolatile memories for 90 nm SoC and beyond” stated as follows: “To maintain high reliability for safety-critical applications, the insulators surrounding the floating gate must be thicker than 100 angstroms if error correction is not employed. This is due to the fact that a single point defect in an insulator is sufficient to create a leakage path through which the entire floating gate charge can leak out.”, EE-Times, http://www.eetimes.com/story/OEG20030317S0057 (2003)